Paper Title
Design and Implementation of High-Performance Logic Arithmetic Full Adder Circuit based on FINFET Technology � Shorted Gate Mode

Abstract
Fin-type field-effect transistors (FinFETs) are promising substitutes for bulk CMOS at the Nano scale. FinFETs are double gate and multi-gate devices. Double-gate (DG) FinFETs has better Short Channels Effects (SCEs) performance compared to the conventional CMOS and stimulates technology scaling. The two gates of a FinFET can either be shorted for higher performance or independently controlled for lower leakage or reduced transistor count. In this paper, we are designing a Double-gate (DG) FinFETs and extracting their transfer characteristics by using Synopsys TANNER-EDA simulation tool. Full Adder is implemented in CMOS with technology and FinFET-shorted gate mode with technology along with its working waveform and performance analysis. TANNER-EDA simulations are carried out for the design and results are analyzed. Keywords - Double-gate FinFET (DG FinFET), Multi-gate (MG), Short channel effects (SCE), Shorted-Gate Mode (SGMode), Drain Induced Barrier Lowering (DIBL), Full Adder.