Paper Title
Design & Analysis of Low Power FinFET based 9T SRAM

Abstract
Power consumption has become a hurdle for recent IC design as the technology is scaled down below 30 nm. SRAMs account for a large fraction of the total power consumption of the chip as they occupy large chip area and have a large activity factor which gives rise to large dynamic power dissipation. A new 9T SRAM cell using FinFET technology is proposed in this paper to improve data stability. The proposed design consumes less power and has better data stability because it provides dual port operation that is different read and write stack for read and write operation, respectively,. The read SNM of the advanced 9T SRAM cell is increased by 16% and hold SNM is increased by 12% as compared to the read SNM & hold SNM of the standard 6T SRAM cell, respectively. Also, the average power of the advanced 9T SRAM cell is decreased by 25% as compared to standard 6T SRAM cell. All simulations are carried out using HSPICE simulator along with Berkeley predictive technology model (BPTM) for multi-gate transistors (PTM-MG) at 7nm, 14nm, 16nm & 20nm technology nodes. Index terms - SRAM, FinFET, HSPICE, Predictive Technology Model.