Paper Title
64bit Multiplier using Vedic Mathematics for DSP Applications

In the as often as possible utilized capacities like Fast Fourier Transform (FFT), Discrete Cosine Transform (DCT), duplication is the essential capacity completed inside. When we consider the speed of execution of these capacities, the most straightforward path for the change is to upgrade the execution of the multiplier units. In this way the execution of quick multiplier will enhance the execution of the present processors. Vedic arithmetic in view of genealogical Indian Vedas gives an alternate duplication calculation to complete quick increase. In rising innovative world the information taking care of limit is a vital element. So the usage of a top of the line processor can have huge effect in the mechanical world. This paper proposes another design for top of the line processor which gives preferable execution over existing models. In this work computerized coding is done in VHDL, amalgamation of the outline is finished by utilizing Xilinx ISE 14.7 and Cadence experience RTL Compiler. Examination of executed computerized framework is finished by utilizing intense rhythm instrument Encounter.