Paper Title
FPGA Implementation of Fault Tolerant Subtractor using Verilog for High Speed VLSI Architectures

Abstract
This research paper presents a fault-tolerant full subtractor design implemented on an Artix 7 FPGA. To enhance reliability and mitigate the effects of hardware failures, the design incorporates self-checking and self-repairing mechanisms. The full subtractor is designed using Verilog and simulated using Vivado to verify its functionality and fault tolerance. The paper discussed the methodologies employed for fault detection, diagnosis, and correction. The self-checking and self-repairing techniques were detailed, highlighting their effectiveness in ensuring the circuit's robustness. Experimental results demonstrated the improved reliability and performance of the fault-tolerant full subtractor on the Artix 7 FPGA. Keywords - Fault Tolerance, VLSI, FPGA, Full Subtractor, Self Checking, Self Repairing, Verilog.