Paper Title
Low-Powerand Area-Efficient CMOS-Based Dadda Multiplier Using Approximate 4:2Compressors for Image Processing and Machine Learning Applications

Abstract
The growing prevalence of battery-powered devices has heightened the need for low-power, area-efficient circuits, with multipliers taking center stage due to their critical role in applications like image processing and machine learning. A small, energy-efficient CMOS-based solution for a 4:2 compressor and Dadda multiplier is presented in this study. The suggested architecture offers notable gains in power efficiency and area reduction by using CMOS logic cells’ multi-input capabilities and transistor-level configurability. Additionally, a unique approximate 4:2 compressor that balances accuracy and power consumption is designed for error-resilient applications. According to CMOS technology simulations, the precise multiplier architecture outperforms conventional designs based on 14nm FinFET technology by achieving a 65% decrease in power usage and a 45% improvement in the power-delay product (PDP). By adding the approximation compressor, the area and PDP are further reduced by 46% and 42%, respectively. Through image multiplication tasks, the efficacy of the suggested design is confirmed, with average PSNR and SSIM values of 31.39 and 0.87, respectively. These findings highlight its potential for processing images in contemporary applications with less energy use Keywords - Low-power, Dadda Multiplier, CMOS, FinFET, PSNR, SSIM.