Paper Title
5-STAGE-PIPELINED-MIPS32- PROCESSOR- DESIGN USING-VERILOG

Abstract
The MIPS32 architecture is widely used in academic and industrial applications due to its simplicity and efficiency. The primary objective of this project is to implement the processor with a 5-stage instruction pipeline consisting of the stages -Instruction Fetch (IF), Instruction Decode (ID), Execution (EX),Memory Access (MEM), and Write Back (WB) to enhance instruction throughput while reducing execution latency through pipelining. The design includes support for key R-type, I-type, and J-type instructions, as well as handling control hazards, data hazards, and pipeline stalls.