Paper Title
A Case Study of Synthesis in VLSI Design Using Fusion Compiler

Abstract
Three main constraints—area, timing, and power consumption—have a major impact on the design flow of Application Specific Integrated Circuits (ASICs) in the field of Very Large Scale Integration (VLSI) design. Addressing these limitations becomes more crucial as these circuits' complexity and performance requirements increase. Electronic Design Automation (EDA) tools, which facilitate several stages of the design process, have been developed to manage this increasing complexity. Logic synthesis is a critical step that converts highlevel Register Transfer Level (RTL) code into an efficient gatelevel netlist. To guarantee that the finished implementation satisfies predetermined performance criteria, this transformation takes design limitations into account. Other factors are introduced when Design for Testability (DFT) methodologies are used during synthesis. Although DFT makes the design more testable, it can also result in higher power and area usage, which could affect performance as a whole. It is crucial to perform performance analysis, which includes comparing the synthesis outcomes under different constraint conditions and with and without DFT insertion. These studies aid in comprehending the trade-offs and in making well-informed judgments to successfully optimize the design. Netlists are legally validated against RTL for Logic Equivalence Checking (LEC) using the Conformal EC tool. A Synopsys EDA tool called Fusion Compiler (FC) offers a convenient way to combine synthesis approaches, reducing design cycles and enhancing design quality. Keywords - VLSI, Synthesis, Logic Equivalence Check(LEC), Fusion Compiler(FC).