Paper Title
DESIGN AND ANALYSIS OF A POWER–PERFORMANCE OPTIMIZED MOS CURRENT-MODE LOGIC DIVIDE-BY-3 PRE-SCALER FOR HIGH-FREQUENCY APPLICATIONS

Abstract
This paper presents the design and analysis of a power–performance optimized divide-by-3 pre-scaler based on MOS current-mode logic (MCML) for high-frequency applications. Frequency prescalers are key components in phase-locked loops and frequency synthesizers, where conventional CMOS implementations often suffer from high power consumption and limited operating speed at gigahertz frequencies. The proposed pre-scaler exploits the constant current steering and reduced voltage swing characteristics of MCML to achieve high-speed operation with improved energy efficiency. A feedback-based differential architecture is employed to realize reliable divide-by-3 functionality while maintaining stable state transitions and low supply noise. Careful optimization of bias current and transistor sizing is performed to minimize the power-delay product and ensure robust performance. Simulation results demonstrate that the proposed MCML-based pre-scaler achieves higher maximum operating frequency and lower power consumption compared to traditional CMOS designs, confirming its suitability for low-power RF and mixed-signal integrated circuit applications. Keywords - MOS Current-Mode Logic, Divide-By-3 Pre-Scalar, Low-Power Design, High-Speed Circuits, Frequency Divider, Power-Delay Product.