Paper Title
CUSTOM RTL DESIGN OF AN APB SLAVE UART MODULE

Abstract
This paper presents the design and physical implementation of a proprietary Universal Asynchronous Receiver/ Transmitter (UART) featuring an AMBA Advanced Peripheral Bus (APB) slave interface. When connecting parallel, high-speed Modern System-on-Chip (SoC) architectures often have problems with communication between on-chip buses and slower, serial devices that are outside of the chip. To solve this problem, we made a synthesizable, lightweight RegisterTransfer Level (RTL) IP core which works as a reliable data bridge. The Verilog-written module contains a baud rate generator that can be changed, separate Transmit (TX) and Receive (RX) circuits, and internal FIFOs to keep data from safe during transfer. We first used strict testbenches and waveform analysis in Xilinx Vivado to test the design’s most important parts, like an internal loopback self-verify mode and a standard 8-N-1 frame format. To show that the whole system worked in the real world, it was then put on a Zed Board. We were able to connect the UART to an external GPS module, that showed us the system could process live, asynchronous serial data, reliably deserialize it over the APB bridge, and also shows the readable output in real time on a PuTTY terminal. These hardware results show that this kind of APB-UART module is a strong, modular, and highly reusable way to connect sensors without any problems. Keywords - RTL Design, UART, APB Slave, Verilog HDL, AMBA, System-on-Chip (SoC), FPGA, Xilinx Vivado, Serial Communication, FIFO, GPS Interfacing, ZedBoard, Real-Time Hardware Implementation