Paper Title
RTL Design and Functional Verification of Sram Interface Using an AHB–APB Bridge for Efficient Read and Write Data Communication

Abstract
The complexity of System-On-Chip (SoC) architectural designs requires an efficient mechanism for effective interaction between high-speed system buses and lowpower peripheral components. Advanced High-performance Bus (AHB) and Advanced Peripheral Bus (APB), based on AMBA architecture, are common solutions to such requirements. In this paper, the RTL implementation and verification of SRAM interface designed as APB slave and connected via AHB–APB bridge are presented to enable efficient read/write data transfer. The architecture proposed provides proper interaction and protocols conversion between AHB master working at a high speed and APB-based SRAM peripheral device. The APB slave interface is added into the SRAM device itself in order to provide proper mapping and communication of signals. The key issue considered while designing is proper addressing decoding and control of access timing, ensuring efficient and reliable data access. The complete design model was made using Verilog HDL and tested by various directed and random test scenarios. Simulated data shows proper conversion of protocols, efficiency of read/write transactions, and reliability of data transfer without data losses. Keywords - SRAM Interface, AHB–APB Bridge, AMBA Architecture, RTL Design, Functional Verification, APB Slave, Verilog HDL, Read/Write Data Transfer, Efficient Data Communication, SoC