Paper Title
Performance Analysis of a 3GHz Voltage Controlled Ring Oscillator In 180nm CMOS Technology

Abstract
This paper presents the design and analysis of a 3 GHz voltage-controlled ring oscillator implemented in 180-nm CMOS technology. The circuit was designed and simulated using 1.8 V supply voltage in the Cadence Virtuoso environment.The implemented oscillator utilizes a three-stageinverter-based architecture with output buffer stages to produce stable high frequency operation. The 3 GHz ring oscillator design focuses on its phase noise and jitter across various process corners. In this study under typical-typical (TT) Conditions, the oscillator achieves a frequency of 3 GHz.Phase noise at a 500kHz offset is measured at -72.98dBc/Hz and -75.99dBc/Hz.The performance is analyzed using transient analysis, periodic steady state (PSS) analysis, phase noise analysis, and process corner analysis under TT, FF, and SS operating conditions. This 3 GHz voltage voltage-controlled ring oscillator is ideal for high-speed communication, PLLs and frequency synthesizers applications. Keywords - Voltage-Controlled Ring Oscillator (VCRO), PLL, Phase Noise, Process Corner Analysis