Paper Title
Design and Implementation of 32-Bit Risc Processor with Five Stage Pipeline

Abstract
Pipeline processor is a processor that applies to the single cycle architecture. It executes single instructions simultaneously, improving throughput significantly. It must add logic to handle dependencies between simultaneously executing instructions. The proposed research work is the design of a 32-bit RISC (Reduced Instruction Set Computer) processor. The design helps to improve the speed of processor, and to give the higher performance of the processor. It has 5 stages of pipeline viz instruction fetch, instruction decode, instruction execute, memory access and write back all in one clock cycle. All the modules in the design are coded in Verilog HDL. Keywords - Processor, Reduced Instruction Set Computer (RISC), FPGA, Xilinx 14.5, ModelSim 6.5e