Energy Efficient FinFET based SRAM Design in 22-Nanometer Technology
In this paper a FinFET based 8T SRAM design is presented on 22nm technology. This circuit is mainly governed by the control switch CS, which is highly responsible for reduction in leakage current, thus resulting in a very low leakage power of 0.331pW. Also, this design utilizes the functioning of a read buffer, which results in improved read delay of 0.16ns, reduced read current of 4.838µA along with enhancing the Read Static Noise Margin (RSNM) with a value of 495mV, thus enhancing the reading ability of the circuit and operating at a minimal voltage of 70mV. It also explains the energy efficiency of the circuit in read and write modes, thus also greatly improving the average energy consumption of 1.2fJ of the circuit.
Keywords - CMOS integrated circuits; FinFET; High speed; Leakage currents; Low power; Nanotechnology; SRAM cells; Very large scale integration (VLSI).