Paper Title
A Novel Architecture of High Speed and Low Power Network on Chip

Abstract
In System On-chip(SOC), point to point(p2p) links and buses use to create communication interface between IPs. As technology is shrinking gradually, the complexity of the chip is also proportionally increasing. As a result, a large number of IP cores are required in a single chip. Hence SoCs designs are becoming complex in the modern era. NoCs are getting more popularity to avoid the above-stated problem. In this paper, 5-port new router architecture is implemented. The speed of design is improved by reading data from the input buffer in simultaneous with the routing operation. The NoCs architecture is implemented using Verilog HDL language and synthesized in SAED 90nm technology. The synthesis result shows that the power and speed of the design is improved for 8, 32 and 64 bit. Proposed design provides 21% less delay and 14% less power. Keywords - Network on chip(NoC), System on chip(SoC), Crossbar, Arbiter.