Design and Implementation of Low Delay High Speed 4*4 Bit Multiplier using Partial Sum Addition

Multiplier plays an essential role in digital as well as analog circuits. Multiplication is one of the significant capacities in every single electronic circuit. It is broadly utilized in advanced signal handling (DSP) applications, microcontroller and integrated circuits. There are two types of multiplication algorithms such as, serial multiplication algorithm and parallel multiplication algorithm. Serial multiplication have high complexity and uses in sequential circuits which contain feedback loop while parallel multiplication have low complexity and uses in combinational circuits which did not contain feedback. In this document we purpose a high speed multiplier using pipelining and partial sum addition. We talk about only partial product adder multiplier like Braun Multiplier etc. The multiplier is designed with modified full adder that have less logic and have low delay. The model is simulated using Xilinx 14.7 version and synthesized using RTL compiler. Keyword – Multiplier, Full Adder using Multiplexer, Half adder, Braun Multiplier