Paper Title
Design and Implementation of 8 bit Arithmetic Logic Unit on FPGA using VHDL

Abstract
This paper primarily deals with the design, simulation and implementation of arithmetic Logic Unit (ALU) using Hardware Description Language (HDL) using Xilinx ISE 14.7 and implement them on Field Programmable Gate Array (FPGAs) edge Spartan 6 board to analyze the design parameters.. ALU of digital computers is an aspect of logic design with the objective of developing appropriate algorithms in order to achieve an efficient utilization of the available hardware. The hardware can only perform a relatively simple and primitive set of Boolean & arithmetic operations and are based on a hierarchy of operations that are built by using algorithms employing the hardware. Speed, power and utilization of ALU are the measures of the efficiency of an algorithm. In this paper, we have simulated and synthesized the various parameters of ALUs by using VHDL on Xilinx ISE 14.7 and EDGE SPARTAN 6 FPGA board. Keywords - FPGA, ALU, XILINX, VHDL, SPARTAN 6.