Implementation of Balanced Model Truncation in DSP Filters to Minimize Power and Area using VHDL
Low-power and high efficiency has become the focus of today’s electronics market. This has sparked off research in exploring and comparing new power efficient architectures. This title aims to design and critically compare an FIR filter and its equivalent IIR counterpart in terms of structure, architecture and power dissipation. The final architecture is intended to be targeted to an FPGA and a comparative study of the power dissipation is planned. The scope of this paper is to explore the design of FPGA based parameterized architectures for FIR and equivalent IIR filters derived using the Balanced Model Truncation (BMT) technique. The outcome of this project upon successful completion is twofold: (1) it provides another parameter for the comparison of FIR and IIR filters (2) may help prove the effectiveness of the BMT technique in terms of power. The paper highlights details on how the challenges were tackled in terms of filter design, derivation of the filters using BMT, coefficient quantization, floating point structure simulations, fixing the data path word length and selecting architectures that are suitable for low-power applications using VHDL. The results of the simulations in each case have been described in detail in the appropriate sections.
Keywords - IIR, FIR Filters, BMT-Balanced Model Truncation, VHDL, Area-efficient, Low power, Data Path Design, MATLAB, Xilinx- Vivado and X power ™ - to carry out power comparisons