| CONFERENCE DATE: Hyderabad, India 09-05-2021 |
| Implementation of 32-bit 5-stage Pipelined RISC Processor | |||||||||||
| Page(s): | 29-32 | ||||||||||
| Author | Nayana Yerram, Deepak Ch | ||||||||||
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| Low Complexity Reconfigurable Architecture for Direct Digital Frequency Synthesis | |||||||||||
| Page(s): | 33-36 | ||||||||||
| Author | Ponnana Ramprasad, Ashok Agarwal | ||||||||||
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